This disclosure relates generally to the field of shallow trench isolation (STI) regions that are formed between electrical components on a wafer, and more particularly to STI regions for devices that include trench-based capacitors comprising high-k dielectric and metal plate.
DRAM memory cells include two main components: a storage capacitor, which stores a charge, and an access transistor, which transfers charge to and from the capacitor. The communication between the storage capacitor and the access transistor is controlled by a select signal, commonly referred to as a word line, that connects one plate of the capacitor to a data line, commonly referred to as a bit line. The storage capacitor is typically located in a deep trench that is etched into a wafer comprising a semiconductor substrate. The deep trench design enables a large amount of charge to be stored in a relatively small chip surface area.
Conventional DRAM arrays are organized so that multiple storage cells are positioned as closely as possible to one another. During the operation of the DRAM array, individual memory cells are selected by energizing of the associated word line, causing each of the selected cells to communicate their contents to sense amplifiers by way of their respective associated bit lines. In order for the DRAM array to function properly, it is essential to electrically isolate the memory cells from one another. Since current research is directed toward a greater density of memory cells per unit of semiconductor substrate, effective isolation means is important.
Performance of DRAM arrays is related to the speed of data access and data writing, and to the power consumption of the DRAM. The power consumption is dependent on the rate at which stored data need to be refreshed due to a gradual loss of stored charge from the storage capacitors through various leakage mechanisms or leakage currents. Data read and write speeds are affected by the parasitic resistance of various elements that may slow down charge transfer to and from the storage capacitors. As the memory density increases, the parasitic resistance rises, causing a drop in performance. Similarly, the storage capacitance and amount of stored charge decreases for scaled down cells, forcing faster data refresh rates and increased power consumption. The use of low-resistance and high-dielectric-constant materials provides means for alleviating the performance drop in scaled down cells.
Embedded DRAM arrays (eDRAM) are conventional DRAM arrays built alongside a fast-switching logic circuitry, allowing for vast amounts of memory to be placed in immediate proximity to high-speed microprocessor cores and other logic elements, collective referred to as logic. The eDRAM microstructure and fabrication processes should be compatible with the logic microstructures and fabrication processes. More specifically, a trench-based eDRAM microstructure must be able to withstand exposure to thermal steps that may be used in a logic fabrication process without adverse effects in the eDRAM.
Trench-based capacitors are also used as decoupling capacitors in various types of integrated circuits (ICs). Individual trench-based capacitors may be arranged into regular arrays, similar to those that are used in DRAM cells, but without access transistors. Such decoupling capacitor arrays allow for a large capacitance to be packed in relatively small chip area providing increased noise immunity in chip power and ground lines.
Such trench-based capacitors may be isolated by shallow trench isolation (STI) regions that are formed between the deep trench capacitors. An STI region is a vertical trench that is etched into an electrically active portion of a wafer and filled with oxide. A liner is typically formed in an STI trench after the trench is etched to smooth the interior and the corners of the STI trench. Another purpose of the liner is to provide a high-quality isolation-semiconductor interface with low density of mid-gap states (Dit), to ensure a low leakage current in the transistor off state and better reliability with reduced hot carrier effects. Since higher temperature oxidation processes are known for low-Dit interfaces and corner rounding effects, formation of the liner is typically a high temperature process (for example, over 900° C.). The formation of STI oxide fill may also be performed at a relatively high temperature.
During formation of the oxide-filled STI regions, including the liner, in a wafer that includes deep-trench capacitors, low-resistance and high-dielectric-constant materials that make up the capacitors may be oxidized. Oxidized materials cause higher parasitic series resistance and structural defects in the adjacent substrate. Higher series resistance reduces memory performance. Structural defects result in electrical leakage between memory elements and may also interact with downstream thermal steps causing permanent wafer distortion and warping, which may degrade the quality of the lithography overlay between subsequent printed layers reducing yield of the manufacturing process.